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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. lm5164-q1 snvsb51 ? september 2018 lm5164-q1 100-v input, 1-a synchronous buck dc/dc converter with ultra-low i q 1 1 features 1 ? aec-q100 qualified for automotive applications ? device temperature grade 1: ? 40 c to 125 c, ambient temperature range ? designed for reliable and rugged applications ? wide input voltage range of 6 v to 100 v ? junction temperature range: ? 40 c to 150 c ? fixed 3-ms internal soft-start timer ? peak and valley current limit protection ? input uvlo and thermal shutdown protection ? suited for scalable automotive power supplies ? low minimum on- and off-times of 50 ns ? adjustable switching frequency up to 1 mhz ? diode emulation for high light-load efficiency ? 10- a no-load input quiescent current ? 3- a shutdown quiescent current ? optimized for cispr 25 emi standard ? integration reduces solution size and cost ? cot mode control architecture ? integrated 0.7- nfet buck switch supports wide duty-cycle range ? integrated 0.3- nfet synchronous rectifier eliminates external schottky diode ? 1.2-v 1% internal voltage reference ? no loop compensation components ? internal vcc bias regulator and boot diode ? create a custom design using webench ? power designer 2 applications ? automotive 48-v mild hybrid ecu bias supplies ? automotive dc/dc converters ? automotive hvac compressors and ptc heaters 3 description the lm5164-q1 synchronous buck converter is designed to regulate over a wide input voltage range, minimizing the need for external surge suppression components. a minimum controllable on-time of 50 ns facilitates large step-down conversion ratios, enabling the direct step-down from a 48 v nominal input to low-voltage rails for reduced system complexity and solution cost. the lm5164-q1 operates during input voltage dips as low as 6 v, at nearly 100% duty cycle if needed, making it an excellent choice for high- performance 48 v battery automotive applications and mild hybrid hev/ev systems. with integrated high-side and low-side power mosfets, the lm5164-q1 delivers up to 1 a of output current. a constant on-time (cot) control architecture provides nearly constant switching frequency with excellent load and line transient response. additional features of the lm5164-q1 include ultra-low i q and diode emulation mode operation for high light-load efficiency, innovative peak and valley overcurrent protection, integrated vcc bias supply and bootstrap diode, precision enable and input uvlo, and thermal shutdown protection with automatic recovery. an open-drain pgood indicator provides sequencing, fault reporting, and output voltage monitoring. the lm5164-q1 is qualified to automotive aec-q100 grade 1 and is available in a 8-pin so powerpad ? package. its 1.27-mm pin pitch provides adequate spacing for high-voltage applications. device information (1) part number package body size (nom) lm5164-q1 so powerpad (8) 4.89 mm 3.90 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application typical application efficiency, v out = 12 v v out = 12 v sw bst pgood vin en/uvlo gnd ron fb lm5164-q1 c out 47 f c in 2.2 f v in = 6 v...100 v i out = 1 a l o 68 h *v out tracks v in if v in < 12 v c bst 2.2 nf r fb1 448 k : r fb2 49.9 k : r ron 100 k : u 1 load (a) efficiency (%) 0.001 0.01 0.1 1 30 40 50 60 70 80 90 100 v in = 14v v in = 24v v in = 48v v in = 72v advance information technical documents support &community ordernow productfolder tools & software
2 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics ............................................. 7 7 detailed description .............................................. 8 7.1 overview .................................................................. 8 7.2 functional block diagram ......................................... 9 7.3 feature description ................................................... 9 7.4 device functional modes ........................................ 13 8 application and implementation ........................ 14 8.1 application information ............................................ 14 8.2 typical application .................................................. 14 9 power supply recommendations ...................... 20 10 layout ................................................................... 21 10.1 layout guidelines ................................................. 21 10.2 layout example .................................................... 23 11 device and documentation support ................. 24 11.1 device support ...................................................... 24 11.2 related documentation ....................................... 24 11.3 receiving notification of documentation updates 25 11.4 community resources .......................................... 25 11.5 trademarks ........................................................... 25 11.6 electrostatic discharge caution ............................ 25 11.7 glossary ................................................................ 25 12 mechanical, packaging, and orderable information ........................................................... 25 4 revision history date revision notes september 2018 * initial release advance information
3 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) g = ground, i = input, o = output, p = power 5 pin configuration and functions dda package 8-pin so powerpad top view pin functions pin i/o (1) description no. name 1 gnd g ground connection for internal circuits. 2 vin p/i regulator supply input pin to high-side power mosfet and internal bias regulator. connect directly to the input supply of the buck converter with short, low impedance paths. 3 en/uvlo i precision enable and undervoltage lockout (uvlo) programming pin. if the en/uvlo voltage is below 1.1 v, the converter is in the shutdown mode with all functions disabled. if the uvlo voltage is greater than 1.1 v and below 1.5 v, the converter is in standby mode with the internal vcc regulator operational and no switching. if the en/uvlo voltage is above 1.5 v, the start-up sequence begins. 4 ron i on-time programming pin. a resistor between this pin and gnd sets the buck switch on-time. 5 fb i feedback input of voltage regulation comparator. 6 pgood o power good indicator. this pin is an open-drain output pin. connect to a source voltage through an external pullup resistor between 10 k to 100 k 7 bst p/i bootstrap gate-drive supply. required to connect a high-quality 2.2-nf 50-v x7r ceramic capacitor between bst and sw to bias the internal high-side gate driver. 8 sw p switching node that is internally connected to the source of the high-side nmos buck switch and the drain of the low-side nmos synchronous rectifier. connect to the switching node of the power inductor. ? ep ? exposed pad of the package. no internal electrical connection. solder the ep to the gnd pin and connect to a large copper plane to reduce thermal resistance. advance information vin sw en/uvlo bst gnd ron fb pgood ep
4 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over the recommended operating junction temperature range of ? 40 c to +150 c (unless otherwise noted) (1) min max unit input voltage vin to gnd ? 0.3 100 v en to gnd ? 0.3 100 fb to gnd ? 0.3 5.5 ron to gnd ? 0.3 5.5 bootstrap capacitor external bst to sw capacitance 1.5 2.5 nf output voltage bst to gnd ? 0.3 105.5 v bst to sw ? 0.3 5.5 sw to gnd ? 1.5 100 sw to gnd (20-ns transient) ? 3 pgood to gnd ? 0.3 14 operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates hbm stressing is done in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per aec- q100-002 hbm esd classification level 2, all pins (1) 2000 v charged device model (cdm), per aec- q100-011 cdm esd classification level c4b. all pins except 1, 4, 5, and 8 500 charged device model (cdm), per aec- q100-011 cdm esd classification level c4b. pins 1, 4, 5, and 8 750 v 6.3 recommended operating conditions over the recommended operating junction temperature range of ? 40 c to +150 c (unless otherwise noted) (1) min nom max unit v in input voltage 6 100 v v sw switch node voltage 100 v v en/uvlo enable voltage 100 v i load load current 1 1.25 a f sw switching frequency 1000 khz c bst external bst to sw capacitance 2.2 nf t on programmable on-time 50 10000 ns advance information
5 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953. 6.4 thermal information thermal metric (1) lm5164-q1 unit dda (soic) 8 pins r ja junction-to-ambient thermal resistance 41.1 c/w r jc(top) junction-to-case (top) thermal resistance 37.3 c/w r jb junction-to-board thermal resistance 30.6 c/w jt junction-to-top characterization parameter 6.7 c/w jb junction-to-board characterization parameter 24.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.4 c/w 6.5 electrical characteristics typical values correspond to t j = 25 c. minimum and maximum limits apply over the full ? 40 c to 150 c junction temperature range unless otherwise indicated. v in = 24 v and v en/uvlo = 2 v unless otherwise stated. parameter test conditions min typ max unit supply current i q-shutdown vin shutdown current v en = 0 v 3 a i q-sleep1 vin sleep current v en = 2.5 v, v fb = 1.5 v 10 a i q-active vin active current v en = 2.5 v 660 a en/uvlo v sd-rising shutdown threshold v en/uvlo rising 1.1 v v sd-falling shutdown threshold v en/uvlo falling 0.5 v v en-rising enable threshold v en/uvlo rising 1.47 1.5 1.53 v v en-falling enable threshold v en/uvlo falling 1.37 1.4 1.43 v feedback v ref fb regulation voltage v fb falling 1.188 1.2 1.212 v timing t on1 on-time1 v vin = 12 v, r ron = 75 k 2500 ns t on2 on-time2 v vin = 12 v, r ron = 25 k 830 ns t off-min minimum off-time 50 ns pgood v pg-uth fb upper threshold for pgood high to low v fb rising 1.117 1.14 1.163 v v pg-lth fb lower threshold for pgood high to low v fb falling 1.05 1.08 1.1 v v pg-hys pgood upper and lower threshold hysteresis v fb falling 60 mv r pg pgood pulldown resistance v fb = 1 v 25 bootstrap v bst-uv gate drive uvlo v bst rising 2.6 3 v power switches r dson-hs high-side mosfet r dson i sw = ? 100 ma 0.7 r dson-ls low-side mosfet r dson i sw = 100 ma 0.3 advance information
6 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) typical values correspond to t j = 25 c. minimum and maximum limits apply over the full ? 40 c to 150 c junction temperature range unless otherwise indicated. v in = 24 v and v en/uvlo = 2 v unless otherwise stated. parameter test conditions min typ max unit soft start t ss internal soft-start time 2.5 3 4 ms current limit i peak1 peak current limit threshold (hs) 1.3 1.5 1.7 a i peak2 peak current limit threshold (ls) 1.3 1.5 1.7 a i delta-ilim min of (i peak1 or i peak2 ) minus i valley 150 ma i valley valley current limit threshold 1 1.2 1.4 a thermal shutdown t sd thermal shutdown threshold t j rising 175 c t sd-hys thermal shutdown hysteresis 10 c advance information
7 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 typical characteristics at t a = 25 c, v out = 12 v, l o = 68 h, r ron = 125 k , unless otherwise specified. v out = 12 v see figure 3 figure 1. conversion efficiency (log scale) v out = 12 v see figure 3 figure 2. conversion efficiency (linear scale) load (a) efficiency (%) 0.001 0.01 0.1 1 30 40 50 60 70 80 90 100 v in = 14v v in = 24v v in = 48v v in = 72v load (a) efficiency (%) 0 0.2 0.4 0.6 0.8 1 60 70 80 90 100 v in = 14v v in = 24v v in = 48v v in = 72v advance information
8 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the lm5164-q1 is an easy-to-use, ultra-low i q constant on-time (cot) synchronous step-down buck regulator. with integrated high-side and low-side power mosfets, the lm5164-q1 is a low-cost, highly efficient buck converter that operates from a 6 v to 100 v supply voltage delivering up to 1 a dc load current. the lm5164-q1 is available in the 8-pin so powerpad package. this converter, in constant on-time (cot) mode of operation, is ideal for low-noise, high-current, fast load transient requirements, operating with a predictive on-time switching pulse. over the input voltage range, input voltage feedforward is employed to achieve a quasi-fixed switching frequency. a controllable on-time as low as 50 ns permits high step-down ratios and a minimum forced off-time of 50 ns provides extremely high duty-cycles allowing v in to drop close to v out before frequency foldback occurs. at light loads the device transitions into an ultra-low i q mode to maintain high efficiency and prevent draining battery cells connected to the input when the system is in standby. the lm5164-q1 implements a smart peak and valley current limit detection circuit to ensure robust protection during output short circuit conditions. control loop compensation is not required for this regulator, reducing design time and external component count. the lm5164-q1 incorporates additional features for comprehensive system requirements, including an open- drain power good circuit for power-rail sequencing and fault reporting, internally-fixed soft start, monotonic start- up into prebiased loads, precision enable for programmable line undervoltage lockout (uvlo), smart cycle-by- cycle current limit for optimal inductor sizing, and thermal shutdown with automatic recovery. these features enable a flexible and easy-to-use platform for a wide range of applications. the lm5164-q1 supports a wide range of end equipment systems requiring a regulated output from a high input supply where the transient voltage deviates from its dc level. suitable examples of such end equipment systems are 48 v automotive systems, high cell count battery pack systems, 24 v industrial systems, and 48 v telecom and poe voltage ranges. the pin arrangement is designed for a simple layout requiring only a few external components. advance information
9 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.2 functional block diagram 7.3 feature description 7.3.1 control architecture the lm5164-q1 step-down switching converter employs a control circuit that uses a feedback regulation comparator and a programmable one-shot on-timer. the output voltage feedback (fb) is compared to an internal reference (1.2 v). the converter turns on the high-side mosfet with on-time inversely proportional to v in when the fb voltage is less than 1.2 v to operate with a fixed switching frequency when in continuous conduction mode (ccm). diode emulation mode (dem) prevents negative inductor current, and pulse skipping maintains highest efficiency at light load currents by decreasing the effective switching frequency. during a rapid start-up or during a positive load step, the regulator operates with minimum off-times until regulation is achieved. this feature enables extremely fast load transient response with minimum output voltage undershoot. when regulating the output in steady-state operation, the off-time automatically adjusts itself to produce the sw-pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. in ccm the operating frequency is programmed by the r ron resistor and can be calculated using equation 1 . (1) fb vin vdd sw gnd bst ron vdd uvlo on/off timers constant on-time control logic 1.5 v bias regulator v in feedback comparator disable thermal shutdown en/uvlo standby shutdown 0.4 v v cc v in c out v out v out c in c bst r fb1 r fb2 r ron peak/valley current limit vref zc zx detect pgood fb 0.9*vref pgood comparator sleep detect logic + + + + + r uv1 r uv2 l o advance information out sw ron v (v) 2500 f (khz) r (k ) ? :
10 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) diode emulation mode (dem) operation occurs when the synchronous power mosfet switches off as inductor valley current reaches zero. here, the load current is less than half of the peak-to-peak inductor current ripple in ccm. turning off the low-side mosfet at zero current reduces switching loss, and preventing negative current conduction reduces conduction loss. power conversion efficiency is thus higher in a dem converter than an equivalent forced-pwm ccm converter. with dem operation, the duration that both power mosfets remain off progressively increases as load current decreases. when this idle duration exceeds 15 s the converter transitions into an ultra-low i q mode consuming only 10 a queiscent current from the input. 7.3.2 internal vcc regulator and bootstrap capacitor the lm5164-q1 contains an internal linear regulator that powers from vin with a nominal output of 5 v eliminating the need for an external capacitor to stabilize the linear regulator. the internal vcc regulator supplies current to internal circuit blocks including the synchronous fet driver and logic circuits. the input pin (vin) can be connected directly to line voltages up to 100 v. in order to reduce the stress on the internal regulator combined with a low total gate charge on the power mosfet use a low bootstrap capacitor value. it is required to select a high-quality 2.2-nf 50-v x7r ceramic bootstrap capacitor as specified in the absolute maximum ratings . selecting a higher value capacitance stresses the internal vcc regulator and damages the device. a lower capacitance may not be sufficient to drive the internal gate of the power mosfet. an internal diode connects from the linear regulator to the bst pin to replenish the charge in the high-side gate drive bootstrap capacitor when the sw voltage is low. 7.3.3 regulation comparator the feedback voltage at fb is compared to an internal 1.2 v reference. the lm5164-q1 voltage regulation loop regulates the output voltage by maintaining the fb voltage equal to the internal reference voltage, v ref . a resistor divider programs the ratio from output voltage v out to fb. for a target v out setpoint, calculate r fb2 based on the selected r fb1 using equation 2 . (2) ti recommends selecting r fb1 in the range of 100 k to 1 m ? for most applications. a larger r fb1 consumes less dc current, which is mandatory if light-load efficiency is critical. r fb1 larger than 1 m is not recommended as the feedback path becomes more susceptible to noise. it is important to route the feedback trace away from the noisy area of the pcb and keep the feedback resistors close to the fb pin. 7.3.4 internal soft start the lm5164-q1 employs an internal soft-start control ramp that allows the output voltage to gradually reach a steady-state operating point, thereby reducing start-up stresses and current surges. the soft-start feature produces a controlled, monotonic output voltage start-up. the soft-start time is internally set to 3 ms. 7.3.5 on-time generator the on-time of the lm5164-q1 high-side fet is determined by the r ron resistor and is inversely proportional to the input voltage, v in . the inverse relationship with v in results in a nearly constant frequency as v in is varied. calculate the on-time using equation 3 . (3) determine the r ron resistor using equation 4 to set a specific switching frequency in ccm. (4) select r ron for a minimum on-time (at maximum v in ) greater than 50 ns for proper operation. in addition to this minimum on-time, the maximum frequency for this device is limited to 1 mhz. ron on in r k t v v v 2.5 : ? fb2 fb1 out 1.2 v r r v 1.2 v ? out ron sw v (v) 2500 r (k ) f (khz) ? : advance information
11 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.6 current limit the lm5164-q1 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor current. the current sensed in the high-side mosfet is compared every switching cycle to the current limit threshold (1.5 a). current is sensed after a leading-edge blanking time following the high-side mosfet turnon transition. the propagation delay of the current limit comparator is 100 ns. to protect the converter from potential current runaway conditions, the lm5164-q1 includes a fold-back valley current limit feature that is enabled if a peak current limit is detected. if the peak current in the high-side mosfet exceeds 1.5 a (typical), the present cycle is immediately terminated, the high-side mosfet is turned off and the fold-back valley current limit set at 1.2 a is activated. the low-side mosfet remains on until the inductor current drops below this fold-back valley current limit after which the next on-pulse is initiated. this method folds back the switching frequency to prevent overheating and limits the average output current to less than 1.5 a to ensure proper short-circuit and heavy-load protection of the lm5164-q1. during high step-down conditions when the on-time is less than 100 ns (the propagation delay of the high-side current limit comparator), a back-up valley current limit comparator set at 1.5 a enables the fold-back valley current limit set at 1.2 a. this innovative current limit scheme enables ultra-low duty-cylce operation permitting large step down voltage conversions while ensuring robust protection of the converter. 7.3.7 n-channel buck switch and driver the lm5164-q1 integrates an n-channel buck switch and associated floating high-side gate driver. the gate- driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap diode. a high quality 2.2-nf 50-v x7r ceramic capacitor connected between the bst pin and the sw pin provides the voltage to the high-side driver during the buck switch on-time. see internal vcc regulator and bootstrap capacitor for limitations. during the off-time, the sw pin is pulled down to approximately 0 v, and the bootstrap capacitor charges from the internal vcc through the internal bootstrap diode. the minimum off-timer, set to 50 ns (typical), ensures a minimum time each cycle to recharge the bootstrap capacitor. during conditions of small on-times, the minimum off-timer is forced to 250 ns to ensure that the bst capacitor is charged in a single cycle. this is vital during wake up from sleep mode when the voltage across the bst capacitor is most likely discharged. 7.3.8 synchronous rectifier the lm5164-q1 provides an internal low-side synchronous rectifier n-channel mosfet. this mosfet provides a low-resistance path for the inductor current to flow when the high-side mosfet is turned off. the synchronous rectifier operates in a diode emulation mode. diode emulation enables the regulator to operate in a pulse-skipping mode during light load conditions. this mode leads to a reduction in the average switching frequency at light loads. switching losses and fet gate driver losses, both of which are proportional to switching frequency, are significantly reduced at very light loads and efficiency is improved. this pulse-skipping mode also reduces the circulating inductor currents and losses associated with conventional ccm at light loads. 7.3.9 enable/undervoltage lockout (en/uvlo) the lm5164-q1 contains a dual level en/uvlo circuit. when the en/uvlo voltage is below 1.1 v (typical), the converter is in a low-current shutdown mode and the input quiescent current (i q ) is dropped down to 3 a. when the voltage is greater than 1.1 v but less than 1.5 v (typical), the converter is in standby mode. in standby mode the internal bias regulator is active while the control circuit is disabled. when the voltage exceeds the rising threshold of 1.5 v (typical), normal operation begins. install a resistor divider from vin to gnd to set the minimum operating voltage of the regulator. use equation 5 and equation 6 to calculate the input uvlo turn-on and turn-off voltages, respectively. (5) (6) advance information uv1 in(on) uv2 r v 1.5 v 1 r ? ? ? 1 uv1 in(off) uv2 r v 1.4 v 1 r ? ? ? 1
12 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) if input uvlo is not required, the power-supply designer can either drive en/uvlo as an enable input driven by a logic signal or connect it directly to vin. if en/uvlo is directly connected to vin, the regulator begins switching as soon as the internal bias rails are active. 7.3.10 power good (pgood) the lm5164-q1 provides a pgood flag pin to indicate when the output voltage is within the regulation level. use the pgood signal for start-up sequencing of downstream converters or for fault protection and output monitoring. pgood is an open-drain output that requires a pullup resistor to a dc supply not greater than 14 v. the typical range of pullup resistance is 10 k ? to 100 k ? . if necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail. when the fb voltage exceeds 95% of the internal reference v ref , the internal pgood switch turns off and pgood can be pulled high by the external pullup. if the fb voltage falls below 90% of v ref , an internal 25- pgood switch turns on and pgood is pulled low to indicate that the output voltage is out of regulation. the rising edge of pgood has a built-in deglitch delay of 5 s. 7.3.11 thermal protection the lm5164-q1 includes an internal junction temperature monitor to protect the device in the event of a higher than normal junction temperature. if the junction temperature exceeds 175 c (typical), thermal shutdown occurs to prevent further power dissipation and temperature rise. the lm5164-q1 initiates a restart sequence when the junction temperature falls to 165 c, based on a typical thermal shutdown hysteresis of 10 c. this is a non- latching protection, and, as such, the device will cycle into and out of thermal shutdown if the fault persists. advance information
13 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 shutdown mode en/uvlo provides on and off control for the lm5164-q1. when v en/uvlo is below approximately 1.1 v, the device is in shutdown mode. both the internal linear regulator and the switching regulator are off. the quiescent current in shutdown mode drops to 3 a at v in = 24 v. the lm5164-q1 also employs internal bias rail undervoltage protection. if the internal bias supply voltage is below its uv threshold, the regulator remains off. 7.4.2 active mode the lm5164-q1 is in active mode when v en/uvlo is above the precision enable threshold and the internal bias rail is above its uv threshold. in cot active mode, the lm5164-q1 is in one of three modes depending on the load current: 1. ccm with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple 2. pulse skipping and diode emulation mode (dem) when the load current is less than half of the peak-to-peak inductor current ripple in ccm operation 3. current limit ccm with peak and valley current limit protection when an overcurrent condition is applied at the output. 7.4.3 sleep mode control architecture gives a brief introduction to the lm5164-q1 diode emulation (dem) feature. the converter enters dem during light-load conditions when the inductor current decays to zero and the synchronous mosfet is turned off to prevent negative current in the system. in the dem state, the load current is lower than half the peak-to-peak inductor current ripple and the switching frequency decreases when the load is further decreased as the device operates in a pulse skipping mode. a switching pulse is set when v fb drops below 1.2 v. as the frequency of operation decreases and v fb remains above 1.2 v (v ref ) with the output capacitor sourcing the load current for greater than 15 s, the converter enters an ultra-low i q sleep mode to prevent draining the input power supply. the input quiescent current (i q ) required by the lm5164-q1 decreases to 10 a in sleep mode, improving the light-load efficiency of the regulator. in this mode all internal controller circuits are turned off to ensure very low current consumption by the device. such low i q renders the lm5164-q1 as the best option to extend operating lifetime for off-battery applications. the fb comparator and internal bias rail are active to detect when the fb voltage drops below the internal reference v ref and the converter transitions out of sleep mode into active mode. there is a 9 s wake-up delay from sleep to active states. advance information
14 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information as mentioned previously, the lm5164-q1 requires only a few external components to step down from a wide range of supply voltages to a fixed output voltage. several features are integrated to meet system design requirements, including precision enable, input voltage uvlo, internal soft start, programmable switching frequency, and a pgood indicator. to expedite and streamline the process of designing of a lm5164-q1-based converter, a comprehensive lm5164-q1 quickstart calculator is available for download to assist the designer with component selection for a given application. this tool is complemented by the availability of an evaluation module (evm) , numerous pspice models, as well as ti's webench ? power designer . 8.2 typical application for step-by-step design procedure, circuit schematics, bill of materials, pcb files, simulation and test results of an lm5164-q1-powered implementation, see ti designs reference design library. the schematic of a 12-v, 1-a cot converter is shown in figure 3 . figure 3. typical application v in(nom) = 48 v, v out = 12 v, i out(max) = 1 a, f sw(nom) = 300 khz note this and subsequent design examples are provided herein to showcase the lm5164-q1 converter in several different applications. depending on the source impedance of the input supply bus, an electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage and high output current operating conditions. see power supply recommendations for more detail. advance information v out = 12 v sw bst pgood vin en/uvlo gnd ron fb lm5164-q1 c out 47 p f c in 2.2 p f v in = 15 v...100 v i out = 1 a l o 68 p h copyright ? 2018, texas instruments incorporated c bst 2.2 nf r fb1 453 k : r fb2 49.9 k : r ron 100 k : r a 453 k : c a 3.3 nf c b 56 pf u 1
15 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.1 design requirements the target full-load efficiency is 92% based on a nominal input voltage of 48 v and an output voltage of 12 v. the required input voltage range is 15 v to 100 v. the lm5164-q1 delivers a fixed 12 v output voltage. the switching frequency is set by resistor r ron at 300 khz. the output voltage soft-start time is 3 ms. the required components are listed in table 1 . refer to the lm5164-q1evm-041 evm user's guide for more detail. table 1. list of components count ref des value description part number manufacturer 2 c in 2.2 f capacitor, ceramic, 2.2 f, 100v, x7r, 10% cga6n3x7r2a225k230ab tdk 1 c out 22 f capacitor, ceramic, 22 f, 25v, x7r, 10% tmk325b7226kmht taiyo yuden 1 c a 3300 pf capacitor, ceramic, 3300pf, 16v, x7r, 10% cga3e2x7r2a332k080aa tdk 1 c b 56 pf capacitor, ceramic, 100pf, 16v, x7r, 10% 06033c101kat2a avx 1 c bst 2.2 nf capacitor, ceramic, 1000pf, 50v, x7r, 10% cga2b2x7r1h102k050ba tdk 1 l f 68 h inductor, 68 h, 170 m , > 1.8a mss1246t-683mlb coilcraft 1 r ron 100 k resistor, chip, 100 k, 1%, 0.1 w, 0603 rg1608p-1053-b-t5 susumu co ltd 1 r fb1 453 k resistor, chip, 453 k, 1%, 0.1 w, 0603 rt0603brd07448kl yageo 1 r fb2 49.9 k resistor, chip, 49.9 k, 1%, 0.1 w, 0603 rg1608p-4992-b-t5 susumu co ltd 1 r a 453 k resistor, chip, 453 k, 1%, 0.1w, 0603 rt0603brd07453kl yageo 1 u 1 wide v in synchronous buck converter lm5164qddarq1 ti 8.2.2 detailed design procedure 8.2.2.1 custom design with webench ? tools click here to create a custom design using the lm5164-q1 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 8.2.2.2 switching frequency (r ron ) the switching frequency of lm5164-q1 is set by the on-time programming resistor placed at ron. as shown by equation 7 , a standard 100 k , 1% resistor sets the switching frequency at 300 khz. (7) note that at very low duty cycles, the 50 ns minimum controllable on-time of the high-side mosfet, t on(min) , limits the maximum switching frequency. in ccm, t on(min) limits the voltage conversion step-down ratio for a given switching frequency. calculate the minimum controllable duty cycle using equation 8 . (8) ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range, solution size and efficiency. the maximum supply voltage for a given t on(min) before switching frequency reduction occurs is given by equation 9 . out ron sw v (v) 2500 r (k ) f (khz) ? : advance information min on(min) sw d t f ?
16 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (9) 8.2.2.3 buck inductor (l o ) the inductor ripple current (assuming ccm operation) and peak inductor current are given respectively by equation 10 and equation 11 . (10) (11) for most applications, choose an inductance such that the inductor ripple current, i l , is between 30% and 50% of the rated load current at nominal input voltage. calculate the inductance using equation 12 . (12) choosing a 68 h inductor in this design results in 447 ma peak-to-peak ripple current at a nominal input voltage of 48 v, equivalent to 45% of the 1 a rated load current. check the inductor data sheet to make sure the saturation current of the inductor is well above the current limit setting of the lm5164-q1. ferrite-core inductors have relatively lower core losses and are preferred at high switching frequencies, but exhibit a hard saturation characteristic ? the inductance collapses abruptly when the saturation current is exceeded. this results in an abrupt increase in inductor ripple current, higher output voltage ripple, and reduced efficiency in turn compromising reliability. note that inductor saturation current levels generally decrease as the core temperature increases. 8.2.2.4 output capacitor (c out ) select a ceramic output capacitor to limit the capacitive voltage ripple at the converter output. this is the sinusoidal ripple voltage that is generated from the triangular inductor current ripple flowing into and out of the capacitor. select an output capacitance using equation 13 to limit the voltage ripple component to 0.5% of the output voltage. (13) substituting i l(nom) of 447 ma gives c out greater than 3.1 f. with voltage coefficients of ceramic capacitors taken in consideration, a 22- f, 25-v rated capacitor with x7r dielectric is selected. 8.2.2.5 input capacitor (c in ) an input capacitor is necessary to limit the input ripple voltage while providing ac current to the buck power stage at every switching cycle. to minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the vin and gnd pins of the lm5164-q1. the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. it follows that the resultant capacitive component of ac ripple voltage is a triangular waveform. together with the esr-related ripple component, the peak-to-peak ripple voltage amplitude is given by equation 14 . (14) the input capacitance required for a load current, based on an input voltage ripple specification ( vin), is given by equation 15 : out out o sw l in(nom) v v l 1 f i v ? ? ? ? ' ? 1 out in(ripple) out esr sw in i d 1 d v i r f c ? ? ? ? advance information l out sw out(ripple) i c 8 f v ' t ? ? out out l sw o in v v i 1 f l v ' ? ? ? ? 1 l l(peak) out(max) i i i 2 ' out in(max) on(min) sw v v t f ?
17 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (15) choose a high-frequency 100 nf or higher, high-quality x7s or x7r ceramic capacitor with sufficient voltage rating for c in . based on the voltage coefficient of ceramic capacitors, choose a voltage rating of twice the maximum input voltage. additionally, some bulk capacitance is required if the lm5164-q1 is not located within approximately 5 cm from the input voltage source. this capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply lines and high-q ceramics. see power supply recommendations for more detail. 8.2.2.6 type 3 ripple network a type 3 ripple generation network uses an rc filter consisting of r a and c a across sw and v out to generate a triangular ramp that is in phase with the inductor current. this triangular ramp is then ac-coupled into the feedback node using capacitor c b as shown in figure 3 . type 3 ripple injection is suited for applications where low output voltage ripple is crucial. calculate r a and c a using equation 16 and equation 17 to provide the required ripple amplitude at the fb pin. (16) for the feedback resistor values given in figure 3 , equation 16 dictates a minimum c a of 742 pf. in this design, a 3300 pf capacitance is chosen. this is done to keep r a within practical limits between 100 k ? and 1 m ? when using equation 17 . (17) based on c a set at 3.3 nf, r a is calculated to be 453 k ? to provide a 20 mv ripple voltage at fb. the general recommendation for a type 3 network is to calculate r a and c a at typical operating conditions, while ensuring a 12 mv minimum ripple voltage on fb at minimum v in . while the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output regulation as it reflects as a dc error of approximately half the amplitude of the generated ripple. for example, a converter circuit with type 3 network that generates a 40 mv ripple voltage at the feedback node has approximately 10 mv worse load regulation scaled up through the fb divider to v out than the same circuit that generates a 20 mv ripple at fb. calculate the coupling capacitance c b using equation 18 . where ? t tr-settling is desired load transient response settling time (18) c b calculates to 56 pf based on a 75- s settling time. this value avoids excessive coupling capacitor discharge by the feedback resistors during sleep intervals when operating at light loads. to avoid capacitance falloff with dc bias, use a c0g or np0 dielectric capacitor for c b . tr-settling b fb1 t c 3 r t ? in(nom) out on(nom) a a v v t r c 20mv ? t a sw fb1 fb2 10 c f r r t ? out in sw in(ripple) out esr i d 1 d c f v i r ? ? t ? ? advance information
18 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.3 application curves figure 4. conversion efficiency (log scale) figure 5. conversion efficiency (linear scale) figure 6. load and line regulation performance v in = 24 v i out = 0.25 a to 1 a at 0.1 a/ s figure 7. load step response v in = 24 v i out = 0 a figure 8. no-load start-up with vin v in = 24 v i out = 1 a (resistive) figure 9. full-load start-up with vin load (a) efficiency (%) 0.001 0.01 0.1 1 30 40 50 60 70 80 90 100 v in = 14v v in = 24v v in = 48v v in = 72v load (a) efficiency (%) 0 0.2 0.4 0.6 0.8 1 60 70 80 90 100 v in = 14v v in = 24v v in = 48v v in = 72v output current (a) output voltage (v) 0 0.2 0.4 0.6 0.8 1 11.6 11.7 11.8 11.9 12 12.1 12.2 12.3 12.4 v in = 15v v in = 24v v in = 36v v in = 48v v in = 60v advance information
19 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated v in = 24 v i out = 0 a figure 10. no-load start-up and shutdown with en/uvlo v in = 24 v i out = 1 a (resistive) figure 11. full-load start-up and shutdown with en/uvlo v in = 24 v i out = 0 a figure 12. pre-bias start-up with en/uvlo v in = 24 v load = 0 a to short figure 13. short circuit applied v in = 24 v load = short to 0 a figure 14. short circuit recovery v in = 24 v load = 0 a to short to 0 a figure 15. no load to short circuit/short circuit recovery advance information
20 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated v in = 24 v i out = 0 a figure 16. no-load switching v in = 24 v i out = 1 a figure 17. full-load switching 9 power supply recommendations the lm5164-q1 buck converter is designed to operate from a wide input voltage range between 6 v and 100 v. the characteristics of the input supply must be compatible with the absolute maximum ratings and recommended operating conditions tables. in addition, the input supply must be capable of delivering the required input current to the fully-loaded regulator. estimate the average input current with equation 19 . where ? is the efficiency (19) if the converter is connected to an input supply through long wires or pcb traces with a large impedance, take special care to achieve stable performance. the parasitic inductance and resistance of the input cables may have an adverse affect on converter operation. the parasitic inductance in combination with the low-esr ceramic input capacitors form an underdamped resonant circuit. this circuit can cause overvoltage transients at vin each time the input supply is cycled on and off. the parasitic resistance causes the input voltage to dip during a load transient. if the converter is operating close to the minimum input voltage, this dip can cause false uvlo fault triggering and a system reset. the best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. the moderate esr of the electrolytic capacitor helps to damp the input resonant circuit and reduce any voltage overshoots. a 10- f electrolytic capacitor with a typical esr of 0.5 provides enough damping for most input circuit configurations. an emi input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. the application report simple success with conducted emi for dc-dc converters (snva489) provides helpful suggestions when designing an input filter for any switching regulator. k? ? in out out in v i v i advance information
21 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines pcb layout is a critical portion of good power supply design. there are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and emi or degrade the power supply performance. 1. to help eliminate these problems, bypass the vin pin to gnd with a low-esr ceramic bypass capacitor with a high-quality dielectric. place c in as close as possible to the lm5164-q1 vin and gnd pins. grounding for both the input and output capacitors should consist of localized top-side planes that connect to the gnd pin and gnd pad. 2. minimize the loop area formed by the input capacitor connections to the vin and gnd pins. 3. locate the inductor close to the sw pin. minimize the area of the sw trace or plane to prevent excessive capacitive coupling. 4. tie the gnd pin directly to the power pad under the device and to a heat-sinking pcb ground plane. 5. use a ground plane in one of the middle layers as a noise shielding and heat dissipation path. 6. have a single-point ground connection to the plane. route the ground connections for the feedback, soft- start, and enable components to the ground plane. this prevents any switched or load currents from flowing in analog ground traces. if not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior. 7. make v in , v out and ground bus connections as wide as possible. this reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 8. minimize trace length to the fb pin. place both feedback resistors, r fb1 and r fb2 , close to the fb pin. place c ff (if needed) directly in parallel with r fb1 . if output setpoint accuracy at the load is important, connect the v out sense at the load. route the v out sense path away from noisy nodes and preferably through a layer on the other side of a grounded shielding layer. 9. the ron pin is sensitive to noise. thus, locate the r ron resistor as close as possible to the device and route with minimal lengths of trace. the parasitic capacitance from ron to gnd must not exceed 20 pf. 10. provide adequate heat sinking for the lm5164-q1 to keep the junction temperature below 150 c. for operation at full rated load, the top-side ground plane is an important heat-dissipating area. use an array of heat-sinking vias to connect the exposed pad to the pcb ground plane. if the pcb has multiple copper layers, these thermal vias must also be connected to inner layer heat-spreading ground planes. 10.1.1 compact pcb layout for emi reduction radiated emi generated by high di/dt components relates to pulsing currents in switching converters. the larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. the key to minimizing radiated emi is to identify the pulsing current path and minimize the area of that path. the critical switching loop of the buck converter power stage in terms of emi is denoted in figure 18 . the topological architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the input capacitor and the integrated mosfets of the lm5164-q1, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing the effective loop area. advance information
22 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) figure 18. dc/dc buck converter with power stage circuit switching loop the input capacitor provides the primary path for the high di/dt components of the high-side mosfet's current. placing a ceramic capacitor as close as possible to the vin and gnd pins is the key to emi reduction. keep the trace connecting sw to the inductor as short as possible and just wide enough to carry the load current without excessive heating. use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. place the output capacitor close to the v out side of the inductor, and connect the capacitor's return terminal to the gnd pin and exposed pad of the lm5164-q1. 10.1.2 feedback resistors reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the fb pin, rather than close to the load. this reduces the trace length of fb signal and noise coupling. the fb pin is the input to the feedback comparator, and as such is a high impedance node sensitive to noise. the output node is a low impedance node, so the trace from v out to the resistor divider can be long if a short path is not available. route the voltage sense trace from the load to the feedback resistor divider, keeping away from the sw node, the inductor and v in to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. this is most important when high feedback resistances, greater than 100 k , are used to set the output voltage. also, route the voltage sense trace on a different layer from the inductor, sw node and v in , such that there is a ground plane that separates the feedback trace from the inductor and sw node copper polygon. this provides further shielding for the voltage feedback path from switching noise sources. advance information 8 sw vin v out gnd lm5164 low-side nmos gate driver high-side nmos gate driver 1 c in c o q 1 q 2 l o gnd 2 high di/dt loop v in bst
23 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example figure 19 shows an example layout for the pcb top layer of a 2-layer board with essential components placed on the top side. figure 19. lm5164-q1 single-sided pcb layout example advance information connect bst cap close to bst and sw thermal vias under lm5164 pad place fb resistors very close to fb & gnd pins vout connection place rc snubber to reduce sw node rise time pgood connection en/uvlo connection gnd connection place resistor r8 close to the ron pin connect ceramic input cap close to vin and gnd type 3 ripple injection
24 lm5164-q1 snvsb51 ? september 2018 www.ti.com product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.1.2 development support ? lm5164-q1 quickstart calculator ? lm5164-q1 simulation models ? for ti's reference design library, visit tidesigns ? for ti's webench design environment, visit the webench ? design center 11.1.2.1 custom design with webench ? tools click here to create a custom design using the lm5164-q1 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 11.2 related documentation for related documentation see the following: ? lm5164-q1evm-041 evm user ' s guide (snvu620) ? selecting an ideal ripple generation network for your cot buck converter (snva776) ? white papers: ? valuing wide v in , low-emi synchronous buck circuits for cost-effective, demanding applications ? an overview of conducted emi specifications for power supplies ? an overview of radiated emi specifications for power supplies ? ti designs: ? tida-01395 24-v ac power stage with wide v in converter and battery gauge for smart thermostat (tiducw0) ? power house blogs: ? use a low-quiescent-current switcher for high-voltage conversion ? behind the wheel blogs: ? how a dc/dc converter package and pinout design can enhance automotive emi performance ? an-2162: simple success with conducted emi from dc/dc converters (snva489) ? automotive cranking simulator user ' s guide (slvu984) ? using new thermal metrics (sbva025) ? semiconductor and ic package thermal metrics (spra953) advance information
25 lm5164-q1 www.ti.com snvsb51 ? september 2018 product folder links: lm5164-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks powerpad, e2e are trademarks of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 1-nov-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm5164qddarq1 preview so powerpad dda 8 2500 tbd call ti call ti -40 to 150 LM5164QDDATQ1 preview so powerpad dda 8 250 tbd call ti call ti -40 to 150 pLM5164QDDATQ1 active so powerpad dda 8 250 tbd call ti call ti -40 to 150 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 1-nov-2018 addendum-page 2 other qualified versions of lm5164-q1 : ? catalog: lm5164 note: qualified version definitions: ? catalog - ti's standard catalog product
generic package view images above are just a representation of the package family, actual package may vary. refer to the product data sheet for package details. dda 8 powerpad tm soic - 1.7 mm max height plastic small outline 4202561/g
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